Abstract—This .supply voltage and decrement in power dissipation

Abstract—This research paper analyses the performance of De–Multiplexer (DeMux) using Pass Transistor Logic Configuration, CMOS Logic Configuration (CLC) and basic gate realisation. Furthermore, a comparison between the performances of both the configurations in terms of power dissipation, chip area, power supply and drive current levels are analysed. Besides this, paper also signifies more than 50% decrement in interconnect lengths, chip area and number of transistors count white using pass transistor logic .

configuration in comparison to 1:2 De-Mux implemented with CMOS logic configuration. Moreover, reduction in .supply voltage and decrement in power dissipation up to 60% is observed in pass transistor logic comparing to CMOS logic.Keywords—CMOS logic configuration; De-multiplexer; Passtransistor logic; Power dissipation; Chip area;I. Introduction A de multiplexer (De-Mux) is a combinational digital circuit that has one input and more than one output. it is used when a circuit wishes to send a signal to one of many devices in this paper, the effect of change in architecture of 1:2 de-multiplexer in terms of power dissipation, chip area, supply voltage and output current is analysed. The schematic diagram and characteristic table for 1:2 de-multiplexer is shown in Fig. I , respectively.

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It is observed from the diagram that A :2 de-multiplexer has one input line IN and one select line S, whereas, D0 and D1 are the Two outputs. When S is in logic state 1 (high) output line ..D1 is selected and reflects input at terminal A. Similarly, when S is logic- 0 (low) output line D0  is selected. and Input at IN reaches output line D0. The 1:2de-multiplexer logic is implemented .using gate level configuration that includes two to four logic gate and one inverter circuit.

The observed result indicates that the power dissipation, chip area and other parameters vary with change in transistor technology node or architecture. This research paper analyses the behavior of 1:2 de multiplexer in pass transistor logic and conventional CMOS logic architecture. The Technology node and supply voltages of 130nm and 5V are considered from .experimental results respectively so that all architecture/configurational impact can be measured significantly with respect to different architectures.

The results show that the 1:2 de-multiplexer logic implementation in pass transistor logic architecture perform better in comparison to CMOS logic configuration mainly in terms of area consumption, number of transistor counts, supply voltage and power dissipation.II. CMOS LOGIC IMPLEMENTATION ?CMOS logic architecture is one of the most commonly used logic configuration employed in digital circuit designing but it has its own merits and demerits.

Few are described here such as large numbers of transistors are required even to implement simple circuits like basic logic gates and inverter circuit. Fig. 2 depicts CMOS architecture of 1:2 de-multiplexers. It is dear from the diagram that 14 transistors are required to implement this device. Six transistors for each AND gate and two for NOT gate, where S. is selection line. The IN is input that is applied to both the AND gates.

D0 and D1 represent output tines. The selection of these lines is dependent on terminal S It can also be understood from the figure that large number of interconnects are used in this approach to connect -numerous transistors. Therefore, CMOS logic is easy to design but very resource consuming.III. BASIC GATE REALISATIONA 1:2 demultiplexer consists of one input line, two output lines and one select line. The signal on the select line helps to switch the input to one of the two outputs. The figure below shows the block diagram of a 1-to-2 demultiplexer with additional enable input. The figure above shows the 1:2demux which consist of 4 and gate and 2 inverters.

3 PASS TRANSISNOR LOGIC ARCHiTECTUREThe implementation of 1:2 de-multiplexer using pass transistor logic configurations is required only six transistors to implement the complete logic architecture. This means that number of transistors used in pass transistor architecture is less than 50% (half) of the transistors utilized in CMOS architecture. Therefore, it is evident from the facts stated. Figure 3, show that the area consumption is 50% less using pass transistor logic architecture. Moreover, lesser interconnect lengths and fewer transistors allows a decrement in fabrication cost too.

Moreover; the fabrication steps and resources are also decreased/ consumed less in pass transistor logic implementation. Therefore, results observed in both the architecture is stated that pass transistor architecture is more area efficient than ordinary CMOS architecture.IV.

ANALYSIS OF POWER DISSIPATION AND PERFORMANCE COMPARISON FOR CMOS AND PASS TRANSISTOR LOGICThe Power dissipation is the most important characteristic of any device in the era of portable devices, where most of the systems are working on a battery that has limited supply/backup time. Moreover, battery technology is not been able to cope-up with the transistor technology changes in recent times due to which a rift has been generated between power consumed by the device and power available to use. This gap can be fulfilling by the low power VLSI design methodologies that can reduce the power dissipation of the devices.

CMOS is power efficient logic but it can deduce that 1:2 De-multiplexer design implementation using pass transistor logic can further reduce the power dissipation of the circuits. Since CMOS logic implementation requires larger number of transistors therefore operating point is higher in CMOS logic implementation than the pass transistor logic implementation.V. CONCLUSIONThis paper analyzed the performance of 1:2 De-Mux using PTLA and CIA. The results observed that approximately 50% of chip area is saved by using the pass transistor logic configuration as only six transistors (6-T) are employed to implement the 1:2 de-multiplexer while fourteen transistors (14-T) are used in CMOS logic architecture. The power supply is reduced by 33% observed due to processes with pass transistor logic. Moreover, 60% reduction in power dissipation is analyzed with pass transistor. Therefore, it can be concluded that the pass transistor logic implementation of 1:2 de-multiplexer gives better performance and consumes less chip area in comparison to CMOS logic architectureReferences1 M.

D. Ciletti and M. Morris Mano: Digital design, 4th Ed.,        Pearson, India, 2009.2 J M. D. Ciletti and M.

Morris Mano: Digital design, 4thEd., Pearson, India, 2009..3 S. Byun, J. C. Lee, J. H.

Shim, K. Kim and H. K. Yu, “A 10G-b/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector”, IEEE Int.

Solid-State Circuits Conf (ISSCC 2006) Tech. Digest, pp. 1324-1333, San Francisco, CA, USA 6-9 Feb. 2006.K.

Elissa, “Title of paper if known,” unpublished.4 Arun Pratap Singh Rathod, Praveen Lakhera, A. K. Baliga, Poornima Mittal and Brijesh Kumar.” Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers” International Conference on Computing, Communication and Automation (ICCCA2015) 2015 IEEE.5    S.

R. Whitaker, “Combinational logic structures using pass        transistors”, United States Patent, Patent No. 4,541,067, 1985.

6    D. A. Pucknell and K. Eshraghian, “Basic VLSI design”, 3rdEd, Prentice-Hall, India, 2006.